Digital to analog converter with step voltage generator for smoothing analog output

ABSTRACT

A digital-to-analog converter for generating output waveforms with less distortion without the need for high-speed components. The digital-to-analog converter comprises four data holding sections, four step function generators, an adding section, a D/A converter, two integrators and a timing controller. Four digital data successively inputs are held in the data holding sections, respectively, and the step function generators generate step function whose values corresponding to the held data. The adding section sums the step functions generated in the step function generators, and the D/A converter generates the analog stepwise voltage corresponding to the summed value. The two integrators integrate this combined waveform two times, thus producing a continuous analog voltage that connects the input digital data smoothly.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital-to-analog converter forconverting discrete digital data into continuous analog signals. In thisspecification, it is assumed that a case where function values havefinite values except zero in a local region and become zero in regionsdifferent from the region is called a “local support.”

2. Description of the Prior Art

A recent digital audio apparatus, for example, a CD (Compact Disk)player, uses a D/A (digital-to-analog) converter to which anover-sampling technique is applied to obtain a continuous analog audiosignal from discrete music data (digital data). Such a D/A convertergenerally uses a digital filter to raise a pseudo sampling frequency byinterpolating input digital data, and outputs smooth analog voicesignals by passing each interpolation value through a low-pass filterafter generating a staircase signal waveform with each interpolationvalue held by the sample holding circuit.

A data interpolating process is performed with a digital filtercontained in a D/A converter using a sampling function generallyreferred to as a sinc function. FIG. 13 is an explanatory graph of asinc function. This sinc function is obtained when a Dirac deltafunction is inverse-Fourier-transformed, and is defined as sin(πft)/(πft) where the sampling frequency is f. This sinc functionbecomes one only at a sample point, where t=0, and zero at all othersample points.

Conventionally, an oversampling process is performed using a digitalfilter in which a waveform data of the sinc function is set to a tapcounter of an FIR (finite impulse response) filter.

In the oversampling technology for performing an interpolating operationon discrete voice data using a digital filter, a low-pass filter havinga moderate attenuation characteristic can be applied. Therefore, thephase characteristic with a low-pass filter can approach a linear phasecharacteristic, and the sampling aliasing noise can be reduced. Such aneffect becomes more outstanding with a higher pseudo sampling frequency.However, when a sampling frequency rises, the processing speed of thedigital filter and the sample holding circuit is also increased.Therefore, expensive parts applied in the high-speed process arerequired, thereby raising the entire parts cost. In addition, when ahigh sampling frequency (for example, several MHz) is necessary forimage data, etc., a digital filter for oversampling and a sample holdingcircuit have to be mounted using parts operated around several ten MHzto several hundred MHz, which cannot be easily realized.

In addition, even when the oversampling technology is used, a smoothanalog signal is generated by passing a staircase signal waveformthrough a low-pass filter. Therefore, when a low-pass filter is used, alinear phase characteristic in the strict sense cannot be expected.Furthermore, the above mentioned sinc function is a function convergingto 0 at ±∞. Therefore, when a correct interpolation value is computed,all digital data values should be considered. However, for convenienceof a circuit size, etc., the number of tap counters of a digital filteris set so as to the range of digital data to be taken into account islimited. Therefore, an obtained interpolation value contains atruncation error.

Thus, the conventional D/A converter using the oversampling technologyrequires parts for a high-speed operation to raise a pseudo samplingfrequency, thereby incurring a high cost or realizing a necessary systemwith difficulty. Furthermore, the deterioration of the phasecharacteristic arises from using a low-pass filter, and a truncationerror is contained because the digital filter to which a sinc functionis applied is used. Therefore, distortion of output waveform accordingto the deterioration of the phase characteristic and the truncationerror occurs.

BRIEF SUMMARY OF THE INVENTION

The present invention has been developed based on the above mentionedproblems, the object of the present invention is to provide adigital-to-analog converter capable of obtaining an output waveform withless distortion without increasing the speed of operating parts.

A digital-to-analog converter of the invention generates a predeterminedstep functions having a value corresponding to respective input digitaldata and adds the step functions into a step wise analog voltage, andmakes the analog integral operations multiple times to produce acontinuous analog signal that connects smoothly the voltagescorresponding to the digital data input successively. In this way, astep function corresponding to each of a plurality of digital data inputsuccessively is generated, and the values of the step functions areadded. Thereafter, the result of addition is converted into an analogvoltage and integrated to get a continuous analog signal. Therefore,there is no need of using a low-pass filter to get a final analogsignal. Therefore, there is no deterioration of the group delaycharacteristic caused by variable phase characteristic depending on thefrequency of a signal to be processed, resulting in an output waveformwith less distortion. Also, since there is no need of speeding up theoperation rate of parts, and using expensive parts, unlike theconventional method that performed the oversampling, it is possible toreduce the part costs.

In particular, the above-described step function is preferably obtainedby differentiating a sampling function consisting of a piecewisepolynomial multiple times. On the contrary, the waveform correspondingto the predetermined sampling function can be obtained by integratingthis step function multiple times. Therefore, the convolution operationusing the sampling function can be equivalently performed generating thestep function, so that the processing contents can be simplified, andthe volume of processing required for converting digital data to analogsignal can be reduced.

The above-described sampling function is preferably differentiable onlyonce over the whole range, and has values of a local support. It isconsidered that it is necessary that various signals existing in thenatural world have differentiability because the signals changesmoothly. Nevertheless, it is considered that it is not necessary thatthe differentiability is not always infinite, and that it is possible tosufficiently approximate natural phenomena so long as the signals can bedifferentiated only once. In this manner, although there are manyadvantages by using a sampling function of the local support that can bedifferentiated finite times, conventionally, it was considered that asampling function fulfilling these conditions did not exist.Nevertheless, by the present inventor's research, a function fulfillingthe conditions described above is found.

More specifically, the above-described sampling function is a functionof local support having the values other than zero in a range where thesample point t is from −2 to +2. This sampling function is defined suchthat:

(−t ²−4t−4)/4 for −2≦t<−3/2,

(3t ²+8t+5)/4 for −3/2≦t<−1,

(5t ²+12t+7)/4 for −1≦t<1/2,

(−7t ²+4)/4 for −1/2≦t<1/2,

(5t ²−12t+7)/4 for 1/2≦t<1,

(3t ²−8t+5)/4 for 1 ≦t<3/2,

and

(−t²+4t−4)/4 for 3/2≦t≦2

Or a step function waveform corresponding to such a sampling functionmay consist of eight piecewise sections in equal width with a weight of−1, +3, +5, −7, −7, +5, +3, and −1 in a predetermined rangecorresponding to five digital data arranged at an equal interval. Thisweighting process is preferably implemented by adding digital dataitself to the result of multiplication of −2, +2, +4, −8, −8, +4, +2, −2with a bit shift. Since the multiplication operation is performed by thebit shift, the simplified and fast processing can be effected.

In this way, the use of a sampling function differentiable only onceover the whole range, the number of integrating operation after adding aplurality of a step function can be decreased,and the amount ofcalculation can be reduced. Also, because of the use of a samplingfunction having values of a local support, it is possible to handle onlydigital data corresponding to a section for the local support, so thatthe amount of calculation can be further reduced. Moreover, it ispossible to prevent the truncation error from arising when the processis performed for the finite number of digital data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an explanatory graph of a sampling function used for aninterpolating operation of a D/A converter according to an embodiment;

FIG. 2 is a graph showing a relation of the sampled values with aninterpolated value between them;

FIGS. 3A to 3D are graphs for explaining the data interpolation usingthe sampling function shown in FIG. 1;

FIG. 4 is a graph showing a waveform in which the sampling functionshown in FIG. 1 is differentiated once;

FIG. 5 is a graph showing a waveform in which a polygonal function shownin FIG. 4 is further differentiated;

FIG. 6 is a block diagram showing the configuration of a D/A converterof an embodiment;

FIGS. 7A to 7L are charts showing the operation timings of the D/Aconverter of an embodiment;

FIG. 8 is a diagram showing a detailed configuration of the D/Aconverter shown in FIG. 6;

FIG. 9 is a diagram showing a detailed configuration of the stepfunction generator;

FIG. 10 is a chart showing the relation between a varied step functionand the ON/OFF switching timings of each tri-state buffer within thestep function generator;

FIG. 11 is a diagram showing a detailed configuration of a timingcontroller;

FIG. 12 is a chart showing the operation timings of the timingcontroller shown in FIG. 12; and

FIG. 13 is an explanatory graph of a sinc function.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The D/A converter according to an embodiment of the present inventionwill be described below with reference to the drawings. FIG. 1 is anexplanatory graph of a sampling function used for an interpolatingoperation of a D/A converter according to an embodiment. A samplingfunction H(t) shown in FIG. 1 is a function of a local support to whichattention is paid on differentiability. For example, the function H(t)can be differentiated only once in the whole region and a function of alocal support having finite values, which are not zeroes, when a sampleposition along a horizontal axis is between −2 and +2. In addition,since being a sampling function, the function H(t) is characterized inthat the function H(t) becomes one only at a sample point with t=0 andbecomes zero at sample points with t=±1 and ±2.

It is verified by the present inventor's investigation that a functionH(t) fulfilling various conditions described above (a sampling function,one-time differentiability, and a local support) exists. Concretely,with letting a third order B spline function be F(t), such a samplingfunction H(t) can be defined as:

H(t)=−F(t+1/2)/4+F(t)−F(t−1/2)/4  (1)

where F(t) is a third order B spline function.

Here, the third order B spline function F(t) is expressed as:$\begin{matrix}\begin{matrix}{{\left( {{4t^{2}} + {12t} + 9} \right)/4};} & {{{- 3}/2} \leq t < {{- 1}/2}} \\{{{{- 2}t^{2}} + {3/2}};} & {{{- 1}/2} \leq t < {1/2}} \\{{\left( {{4t^{2}} - {12t} + 9} \right)/4};} & {{1/2} \leq t < {3/2}}\end{matrix} & (2)\end{matrix}$

The above-described sampling function H(t) is a quadric piecewisepolynomial, and uses the third order B spline function F(t). Therefore,the function H(t) is a function of a local support that is guaranteed tobe differentiable only once over the whole region. In addition, thefunction H(t) becomes zero at t=±1 and ±2.

Substituting the expression (2) into (1), the sampling function H(t) isrepresented in the form of a piecewise polynomial such that:$\begin{matrix}\begin{matrix}{{\left( {{- t^{2}} - {4t} - 4} \right)/4};} & {{- 2} \leq t < {{- 3}/2}} \\{{\left( {{3t^{2}} + {8t} + 5} \right)/4};} & {{{- 3}/2} \leq t < {- 1}} \\{{\left( {{5t^{2}} + {12t} + 7} \right)/4};} & {{- 1} \leq t < {{- 1}/2}} \\{{\left( {{{- 7}t^{2}} + 4} \right)/4};} & {{{- 1}/2} \leq t < {1/2}} \\{{\left( {{5t^{2}} - {12t} + 7} \right)/4};} & {{1/2} \leq t < 1} \\{{\left( {{3t^{2}} - {8t} + 5} \right)/4};} & {1 \leq t < {3/2}} \\{{\left( {{- t^{2}} + {4t} - 4} \right)/4};} & {{3/2} \leq t \leq 2}\end{matrix} & (3)\end{matrix}$

In this manner, the above-described function H(t) is a sampling functionand a function of a local support that can be differentiated only onceover the whole region and converges to zero at sample point t=±2.Therefore, it is possible to perform interpolation of a value betweensample values using a function, which is differentiable only once, byperforming convolution on the basis of respective sample value usingthis sampling function H(t).

FIG. 2 shows the relationship between sample value and interpolationvalues between the sample values. Generally, to obtain an interpolationvalue y corresponding to intermediate position between each samplevalue, the value of a sampling function is obtained for each piece ofthe given sample value at the position of the interpolation value, and aconvolution operation is performed using the obtained value.

In order to obtain the interpolation value y accurately, since the sincfunction conventionally used converges to zero at sample points t=±∞, itis necessary to calculate a value of the sinc function at a position ofthe interpolation according to each sample value between t=±∞ andperforming convolution operation using these values. Nevertheless, sincethe sampling function H(t) used in this embodiment converges to zero atsample points with t=±∞2, it is sufficient to consider each two samplevalues before and after an interpolation point. Therefore, it ispossible to drastically reduce operation quantity. In addition, since itis theoretically unnecessary to consider sample value except thatwithout disregarding the sample value in consideration of operationquantity, accuracy, and the like although the sample value should beconsidered, no truncation error arises.

FIGS. 3A to 3D are graphs for explaining the data interpolation usingthe sampling function shown in FIG. 1. Hereinafter, for examples, thesample value Y(t1) at the sample position t1 shown in FIG. 3A will bedescribed concretely. The distance from an interpolation point to t0 asampling position t1 becomes equal to 1+a, when the distance between twoadjacent sampling positions is normalized at 1. Accordingly, when thecentral position of the sampling function H(t) is aligned to thesampling position t1, the value of the sampling function atinterpolation point to becomes equal to H(1+a). Practically, since thepeak height of the center position of the sampling function H(t) isadjusted so that the peak height may coincide with the sample valueY(t1), a value to be obtained becomes a value H(1+a)·Y(t1) obtained bymultiplying the above-described function value H(1+a) by Y(t1).

In the same way, the calculated results H(a)·Y(t2), H(1−a)·Y(t3), andH(2−a)·Y(t4) corresponding to other three sample values are obtained atinterpolation position t0, as shown in FIGS. 3B to 3D. Then, fourcalculated results H(1+a)·Y(t1), H(a)·Y(t2), H(1−a)·Y(t3), andH(2−a)·Y(t4) are added, and convoluted to get an interpolated value y atinterpolation point t0.

In principle, the value of the sampling function H(t) is calculated incorrespondence to each sample value, and convoluted, so that aninterpolated value corresponding to an intermediate position between thesample values can be obtained, as described above. However, the samplingfunction of FIG. 1 is a quadratic piecewise polynomial that isdifferentiable once over the whole region. Using this feature, theinterpolated value can be obtained in accordance with other equivalentprocessing procedures.

FIG. 4 is a graph representing a waveform where the sampling function ofFIG. 1 is differentiated once. Since the sampling function H(t) of FIG.1 is a quadratic piecewise polynomial that is differentiable only onceover the whole region, a polygonal function consisting of continuouspolygonal waveforms as shown in FIG. 4 can be obtained bydifferentiating the sampling function H(t) once.

FIG. 5 is a graph representing a waveform where the polygonal functionof FIG. 4 is further differentiated. However, the polygonal waveform,containing a plurality of corner points, cannot be differentiated overthe entire region, and is differentiated for a linear section betweentwo adjacent corner points. By differentiating the polygonal waveformshown in FIG. 4, a step function consisting of staircase waveforms canbe obtained, as shown in FIG. 5.

In this way, the sampling function for use with the interpolationoperation in the D/A converter of this embodiment is differentiated onceover the whole region to get a polygonal function. Further, thispolygonal function is differentiated over each linear section to get astep function. Accordingly, in reverse order, the step function of FIG.5 is generated and integrated twice, so that a sampling function H(t) ofFIG. 1 can be obtained.

The step function as shown in FIG. 5 has a feature of having an equalarea in the positive region and the negative region, in which the sum ofarea is zero. In other words, if the step function having such featureis integrated by multiple times, a sampling function of a local supportthat is assured to be differentiable over the entire region can beobtained, as shown in FIG. 1.

By the way, in calculating the interpolated value by the use ofconvolution operation shown in FIGS. 3A to 3D, the value of the samplingfunction H(t) is multiplied by each sample value. However, in the casewhere the step function as shown in FIG. 5 is integrated twice to get asampling function H(t), the value of the sampling function obtained bythis integration is multiplied by each sample value, but equivalently,in generating a step function before the integral operations, the stepfunction may be multiplied by each sampled value, and then convoluted,and the thus-obtained result integrated twice to get an interpolatedvalue. The D/A converter of this embodiment calculates the interpolatedvalue in this way, and will be detailed below.

FIG. 6 is a diagram showing a configuration of the D/A converter of thisembodiment. The D/A converter shown in FIG. 6 comprises four dataholding sections 10-1, 10-2, 10-3, 10-4, four step function generators11-1, 11-2, 11-3, 11-4, an adding section 12, a D/A converter 14, twointegrators 16, 18, and a timing controller 20.

Each of the data holding sections 10-1 to 10-4 selects and acceptscyclically the discrete digital data input successively at apredetermined time interval, and holds its value till the next accepttiming has arrived. For example, the digital data input at first is heldin a data holding section 10-1; the digital data input secondly is heldin a data holding section 10-2; the digital data input thirdly is heldin a data holding section 10-3; and the digital data input fourthly isheld in a data holding section 10-4. If the holding operation of data ineach of the data holding sections 10-1 to 10-4 is circulated, the fifthdiscrete data input subsequently is accepted and held in the dataholding section 10-1 that has held the data earliest. In this way, thedigital data input successively is held cyclically in the data holdingsections 10-1 to 10-4.

Each of the step function generators 11-1 to 11-4 generates a stepfunction having an amplitude (crest value) proportional to the value ofheld data in synchronization with the holding timing of digital data inthe corresponding one of the data holding sections 10-1 to 10-4. Thestep function itself has a shape as shown in FIG. 5, and the value ofthis step function is in proportion to the value of digital data held ineach of the data holding sections 10-1 to 10-4. Specific values of thestep function shown in FIG. 5 can be acquired by differentiating eachpiecewise polynomial of the above expression (3) twice and representedas follows. $\begin{matrix}{{- 1};} & {{- 2} \leq t < {{- 3}/2}} \\{3;} & {{{- 3}/2} \leq t < {- 1}} \\{5;} & {{- 1} \leq t < {{- 1}/2}} \\{{- 7};} & {{{- 1}/2} \leq t < 0} \\{{- 7};} & {0 \leq t < {1/2}} \\{5;} & {{1/2} \leq t < 1} \\{3;} & {1 \leq t < {3/2}} \\{{- 1};} & {{3/2} \leq t \leq 2}\end{matrix}$

The adding section 12 adds up digitally the values of the step functionsoutput from four step function generators 11-1 to 11-4. The D/Aconverter 14 generates an analog voltage corresponding to stepwisedigital data input from the adding section 12. Since this D/A converter14 generates a constant analog voltage proportional to the input valueof digital data, an output voltage with the voltage level changingstepwise corresponding to the input digital data is obtained.

Two integrators 16, 18 connected in tandem perform two integraloperations for the stepwise changing output voltage appearing at anoutput end of the D/A converter 14. A linearly changing (like a linearfunction) output voltage is obtained from a former integrator 16, and anoutput voltage changing like a quadratic function is obtained from alatter integrator 18. In this way, if plural digital data are input at afixed interval, the latter integrator 18 outputs a continuous analogsignal with a smooth curve differentiable only once connecting thevoltages corresponding to the digital data.

By the way, since the value of a step function output from a stepfunction generator 11-1 is proportional to the value of digital dataheld in a data holding section 10-1, the voltage value corresponding tothe value of this step function is integrated twice by two integrators16, 18, so that the latter integrator 18 outputs a signal of voltagewaveform corresponding to the result of multiplying the step functionshown in FIG. 1 and the input digital data. Also, the adding section 12adds up the values of the step functions output from the step functiongenerators 11-1 to 11-4. This can be equivalently performed by theconvolution process using a step function as shown in FIG. 1, payingattention to an output signal from the latter integrator 18.

Accordingly, considering the case where the digital data is input at aconstant time interval into the D/A converter of this embodiment, thestart timing of generating the step function waveform in each of thestep function generators 11-1 to 11-4 is shifted corresponding to thisinput time interval. Then, the step functions generated in the stepfunction generators 11-1 to 11-4 are added, and a resulting waveform isconverted into an analog voltage, and integrated twice, to get an analogsignal connecting smoothly the voltages corresponding to the digitaldata input at a fixed interval.

FIGS. 7A to 7L are charts showing the operation timings of the D/Aconverter in this embodiment. As shown in FIG. 7A, if the digital dataD₁, D₂, D₃, . . . are input at a constant time interval, each of thedata holding sections 10-1 to 10-4 accepts and holds these digital dataD₁, D₂, D₃, . . . cyclically. More specifically, the data holdingsection 10-1 accepts a digital data D₁ input at first, and holds digitaldata D₁ till the input digital data is circulated (or till a fifthdigital data D₅ is input) (FIG. 7B). The step function generator 11-1generates a step function having a value proportional to this digitaldata D₁ in accordance with the hold timing of the first digital data D₁(FIG. 7C).

Similarly, the data holding section 10-2 accepts a digital data D₂ inputsecondly and holds the digital data D₂ till the input digital data iscirculated (or a sixth digital data D₆ is input) (FIG. 7D). The stepfunction generator 11-2 generates a step function having a valueproportional to this digital data D₂ in accordance with the hold timingof the second digital data D₂ (FIG. 7E).

The data holding section 10-3 accepts a digital data D₃ input thirdlyand holds the digital data D₃ till the input digital data is circulated(or a seventh digital data D₇ is input) (FIG. 7F). The step functiongenerator 11-3 generates a step function having a value proportional tothis digital data D₃ in accordance with the hold timing of the thirddigital data D₃ (FIG. 7G).

The data holding section 10-4 accepts a digital data D₄ input fourthlyand holds the digital data D₄ till the input digital data D₄ iscirculated (or an eighth digital data D₈ is input) (FIG. 7H). The stepfunction generator 11-4 generates a step function having a valueproportional to this digital data D₄ in accordance with the hold timingof the fourth digital data D₄ (FIG. 7I).

The adding section 12 adds values of step function output from each offour step function generators 11-1 to 11-4 in this way. By the way, thestep function generated by each of the step function generators 11-1 to11-4 as shown in FIG. 5 is a function of a local support having eightpiecewise sections divided at every 0.5 from a region of the samplepoint t=−2 to +2 in which the sampling function of FIG. 1 has finitevalues. For example, a first piecewise section, a second piecewisesection, . . . , and an eighth piecewise section are defined in adirection from the sample point t=−2 to +2.

More specifically, the adding section 12 at first adds a value (3D₁)corresponding to the seventh piecewise section that is generated by thestep function generator 11-1, a value (−7D₂) corresponding to the fifthpiecewise section that is generated by the step function generator 11-2,a value (5D₃) corresponding to the third piecewise section that isgenerated by the step function generator 11-3, and a value (−D₄)corresponding to the first piecewise section that is generated by thestep function generator 11-4 to output a result of addition (3D₁,−7D₂+5D₃−D₄).

Then, the adding section 12 adds a value (−D₁) corresponding to theeighth piecewise section that is generated by the step functiongenerator 11-1, a value (5D₂) corresponding to the sixth piecewisesection that is generated by the step function generator 11-2, a value(−7D₃) corresponding to the fourth piecewise section that is generatedby the step function generator 11-3, and a value (3D₄) corresponding tothe second piecewise section that is generated by the step functiongenerator 11-4 to output a result of addition (−D₁+5D₂−7D₃+3D₄).

In this way, if the stepwise result of addition is output successivelyfrom the adding section 12, the D/A converter 14 generates the analogvoltage based on the result of addition (digital data). Since the D/Aconverter 14 generates a constant analog voltage in proportion to theinput value of digital data, it is possible to get an output waveformhaving a voltage level changing stepwise corresponding to the inputdigital data (FIG. 7J).

If the stepwise voltage level waveform is output from the D/A converter14, the former integrator 16 integrates the waveform to output apolygonal waveform (FIG. 7K). The latter integrator 18 furtherintegrates the polygonal waveform to produce an output voltage with asmooth curve differentiable only once connecting the voltage valuescorresponding to the digital data D₂ and D₃ (FIG. 7L).

In this way, the D/A converter of this embodiment generates a stepfunction in accordance with the holding timing of input digital data,adds up the step functions for four digital data to produce an analogvoltage corresponding to this result of addition, and integrates theresulting analog voltage twice to get a continuous analog signalsmoothly connecting the voltage values corresponding to the digitaldata.

In particular, four step functions are generated corresponding to eachinput digital data at different start timings, the analog voltagecorresponding to the result of addition is generated, and integratedtwice to get a continuous analog signal. Hence, there is no need ofpreparing a sample hold circuit and a low pass filter that wereconventionally required. There is no degradation in the linear phasecharacteristic, whereby the excellent group delay characteristic can beachieved. Since a sampling function H(t) of a local support whichconverges to zero at a sample point t=±2 is used, an interpolationprocess between digital data only uses four digital data, so that theamount of processing required for the interpolation can be diminished.Further, since the oversampling process as conventionally performed isnot conducted, it is only necessary to assure a predetermined operationspeed that is determined depending on the time interval of input digitaldata, and there is no need of effecting particularly fast signalprocessing and using expensive parts.

FIG. 8 is a diagram showing a detailed configuration of a D/A convertershown in FIG. 6. As shown in FIG. 8, each of the data holding sections10-1 to 10-4 is configured by a D-type flip-flop (D-FF), and holds theinput data D₁, D₂, D₃, . . . cyclically by shifting the timing ofaccepting the data input via a buffer 22 one period of the input data.For example, if the digital data of eight bits is input, the 8-bit dataheld in each of the data holding sections 10-1 to 10-4 is input to thecorresponding one of the step function generators 11-1 to 11-4.

FIG. 9 is a diagram showing a detailed configuration of each of the stepfunction generators 11-1 to 11-4. Four step function generators 11-1 to11-4 have the same configuration, and a step function generator 11-1will be only described below in detail.

As shown in FIG. 9, the step function generator 11-1 comprises twotri-state buffers 100, 102 having the inverted output, two tri-statebuffers 104, 106 having the non-inverted output, and an adder (ADD) 108for adding up the data input to the step function generator 11-1 and thedata output via any one of the tri-state buffers 100 to 106.

By the way, the step function shown in FIG. 5 is transformed into a stepfunction shown in FIG. 10 by shifting the horizontal axis +1 upwards.This transformed step function takes a value of 2 to the n-th power.Hence, in the case where the input data is multiplied by a multiplierfactor of each value, the multiplication can be executed through asimple bit shift operation. Thereafter, the horizontal axis shifted +1upwards is restored (or the input data is added to the multipliedresult) to get an output value of each step function generator.

More specifically, a tri-state buffer 100 performs a multiplication of(−2) times by shifting the input data one bit and inversely outputtingeach bit of shifted data, as well as adding 1 to a carry input of theadder 108. At a timing indicated at “S1” in FIG. 10, the datacorresponding to a multiplied result is output from the tri-state buffer100, so that the data corresponding to the first and eighth piecewisesections of the step function can be obtained.

Similarly, a tri-state buffer 102 performs a multiplication of two timesby shifting the input data one bit. At a timing indicated at “S2” inFIG. 10, the data corresponding to a multiplied result is output fromthe tri-state buffer 102, so that the data corresponding to the secondand seventh piecewise sections of the step function can be obtained.

A tri-state buffer 104 performs a multiplication of four times byshifting the input data two bits. At a timing indicated at “S3” in FIG.10, the data corresponding to a multiplied result is output from thetri-state buffer 104, so that the data corresponding to the third andsixth piecewise sections of the step function can be obtained.

A tri-state buffer 106 performs a multiplication of (−8) times byshifting the input data three bits, inverting each bit, and adding 1 toa carry input of the adder 108. At a timing indicated at “S4” in FIG.10, the data corresponding to a multiplied result is output from thetri-state buffer 106, so that the data corresponding to the fourth andfifth piecewise sections of the step function can be obtained.

An adder 108 adds up positive or negative data output selectively fromany one of the tri-state buffers 100 to 106, and the data input to thestep function generator 11-1. And the resulting data from the adder 108is output from the step function 11-1.

The adder 108 follows a different processing procedure depending onwhether the output data of the tri-state buffers 100, 102 being bitshifted and inverted or the output data of the tri-state buffers 104,106 being only bit shifted is input. That is, in the case where theaddition is performed using the data without bit shift, two data aresimply added. On the other hand, in the case where the addition isperformed using the data with bit inverted, two data are added, and thenthe least significant bit b0 is incremented by +1. In order to know towhich category the data input to the adder 108 belongs, it is onlynecessary to investigate whether or not the most significant bit is one.

The adding section 12 shown in FIG. 8 is configured by three adders(ADD) 120, 122, 124 having two input terminals. The data output fromfour step function generators 11-1 to 11-4 are added by these threeadders 120, 122, 124. This result of addition is input to an A/Dconverter (ADC) 14 to be converted into a stepwise voltage waveform, andapplied to the former integrator 16 among two integrators 16, 18connected in tandem.

As shown in FIG. 8, the former integrator 16 comprises two operationalamplifiers 140, 141, two capacitors 142, 143, two resistors 144, 145,and a switch 146. An integration circuit is configured by oneoperational amplifier 140, a capacitor 142 and a resistor 144, andperforms a predetermined integral operation for the output voltage ofthe A/D converter 14 applied to the non-inverted input terminal of theoperational amplifier 140 via the resistor 144. Also, the latterintegrator 18 comprises two operational amplifiers 150, 151, twocapacitors 152, 153, two resistors 154, 155, and a switch 156. Anintegration circuit is configured by one operational amplifier 150, acapacitor 152 and a resistor 154, and performs a predetermined integraloperation for the output voltage of the former integrator 16 applied tothe inverted input terminal of the operational amplifier 150 via theresistor 154.

By the way, the A/D converter of this embodiment is suitable for theuses as a circuit for acquiring the video signal such as an RGB signalor luminance signal of the television receiver, for example. Morespecifically, the A/D converter of the television receiver comprisesthree circuits as configured in FIG. 8 corresponding to each of R, G andB data. The 8-bit R, G and B data are input at a predetermined timeinterval for every scanning line constituting a frame of one screen toproduce continuous R, G and B analog voltages that interpolate betweenthe data.

In a practical integration circuit, the output voltage may be drifted.Therefore, it is preferable to have a circuit for removing the influenceof drift. In this embodiment, a circuit for keeping the average value atzero level is configured by the operational amplifier 141, the capacitor143 and the resistor 145 which are contained in the former integrator16. The voltage level of non-inverted input terminal of the operationalamplifier 140 is adjusted so that the average output value of theintegration circuit configured by the operation amplifier 140 and so onmay be maintained at zero level at any time.

An average level holding circuit is configured by an operationalamplifier 152, a capacitor 153 and a resistor 155 which are contained inthe latter integrator 18. The voltage level of non-inverted inputterminal of the operational amplifier 150 is adjusted so that theaverage output value of the integration circuit configured by theoperation amplifier 150 and so on maybe equal to the voltage levelapplied to the non-inverted input terminal of the operational amplifier151. The voltage level applied to the non-inverted input terminal of theoperational amplifier 151 can be obtained by converting the input datainto an analog voltage, and calculating an average level of the analogvoltage. To obtain this voltage level, there are provided a data holdingsection 180 configured by the D-type flip-flop for holding the inputdata that is input successively, an A/D converter 182 for producing ananalog voltage corresponding to the digital data held, and anintegration circuit 184 for integrating an output voltage of the A/Dconverter 182.

In order to reset electric charges accumulated in an integrationcapacitor of each integration circuit contained in two integrators 16,18 for every frame, the switches 146, 156 are provided and turned onduring a vertical blanking period while a vertical blanking signal issynchronized by a synchronizing circuit 186 configured by the D-typeflip-flop. Then, the capacitor 142 connected to the operationalamplifier 140 and the capacitor 152 connected to the operationalamplifier 150 are discharged respectively to reset the integrationcircuit.

FIG. 11 is a diagram showing a detailed configuration of a timingcontroller 20. As shown in FIG. 11, the timing controller 20 comprises athree-bit counter 160, three exclusive-OR circuits 161 to 163 having thenon-inverted output, two exclusive-OR circuits 164, 165 having theinverted output, three AND circuits 166 to 170 having the non-invertedoutput, and three OR circuits 171 to 173 having the inverted output.

FIG. 12 is a chart showing the operation timings of the timingcontroller 20 shown in FIG. 11. As shown in FIG. 12, the waveforms ofCLK, b0 to b2, c1 to c5, and d1 to d8 appear at positions designated byrespective signs in FIG. 11. As shown in FIGS. 11 and 12, the three-bitcounter 160 performs a counting operation in synchronization with aninput clock signal CLK. The three-bit counter 160 counts up every timethis clock signal rises, and the three-bit outputs b0, b1, and b2 areupdated.

Three switches contained in each of the step function generators 11-1 to11-4 are switched on or off, using the above-described timing controller20, to generate each of the step function shown in FIGS. 7C, 7E, 7G and7I. More specifically, in order to enable the step function generator11-1 to generate a step function shown in FIG. 7C, four tri-statebuffers 100 to 106 within this step function generator 11-1 are switchedon or off depending on the logical states of an output (d3) of an ORcircuit 171, an output (d7) of an AND circuit 169, an output (d2) of anand circuit 167, and an output (d1) of an AND circuit 166, as shown inFIG. 11.

Similarly, in order to enable the step function generator 11-2 togenerate a step function shown in FIG. 7E, four tri-state buffers 100 to106 within this step function generator 11-2 are switched on or offdepending on the logical states of an output (d6) of an OR circuit 173,an output (d8) of an AND circuit 170, an output (d5) of an OR circuit172, and an output (d4) of an AND circuit 168, as shown in FIG. 11.Also, in order to enable the step function generator 11-3 to generate astep function as shown in FIG. 7G, four tri-state buffers 100 to 106within this step function generator 11-3 are switched on or offdepending on the logical states of an output (d7) of an AND circuit 169,an output (d3) of an OR circuit 171, an output (d1) of an AND circuit166, and an output (d2) of an AND circuit 167, as shown in FIG. 11.Also, in order to enable the step function generator 11-4 to generate astep function as shown in FIG. 7I, four tri-state buffers 100 to 106within this step function generator 11-4 are switched on or offdepending on the logical states of an output (d8) of an AND circuit 170,an output (d6) of an OR circuit 173, an output (d4) of an AND circuit168, and an output (d5) of an OR circuit 172, as shown in FIG. 11.

The present invention is not limited to the above-described embodiments,but may be modified in various ways within the scope or spirit of theinvention. For example, in the embodiments described above, the samplingfunction is a function of a local support differentiable only once overthe whole region, but the sampling function may be differentiable twiceor more times. Also, the sampling function of this embodiment convergesto zero at t=±2, as shown in FIG. 1, but may converge to zero at t=±3 orbeyond. For example, in a case of the sampling function converging tozero at t=±3, six data holding sections and six step function generatorsmay be contained in the D/A converter shown in FIG. 6, to generate ananalog voltage connecting smoothly six discrete data by performing aninterpolation process for the discrete data.

Using a sampling function differentiable finite times having values overthe range from −∞ to +∞, rather than a sampling function of a localsupport, an interpolation process may be performed only for pluraldigital data corresponding to finite sample point. For example, if sucha sampling function is defined by a quadratic piecewise polynomial, thestep function waveform can be obtained by differentiating each piecewisepolynomial twice. A voltage is combined using this step functionwaveform, and a resulting voltage is integrated twice to get an analogsignal connecting smoothly the voltages corresponding to the digitaldata.

In the above embodiment, a television receiver is exemplified as oneinstance of using the D/A converter. However, the D/A converter of theinvention may be applied to other uses, such as where digital audio datarecorded on the compact disk or the like is converted into an analogaudio sound.

INDUSTRIAL APPLICABILITY

As described above, with the present invention, a step functioncorresponding to each of plural digital data input successively isgenerated and added, and a result of addition is converted into ananalog voltage and integrated to get an analog voltage that changescontinuously. Accordingly, there is no need of using a low pass filterto obtain an ultimate analog signal. Therefore, there is nodeterioration of the group delay characteristic caused by variable phasecharacteristics depending on the frequency of a signal to be processedand less distortion can be obtained. Also, since there is no need ofspeeding up the operation rate of parts, and using expensive parts,unlike the conventional method that performed the oversampling, it ispossible to reduce the part costs.

What is claimed is:
 1. A digital-to-analog converter comprising agenerator and an integrator, wherein said generator generates apredetermined step function corresponding to each of plural digital datainput at predetermined intervals and generates a continuous analogsignal that connects smoothly between the voltages corresponding to theplural digital data by use of said integrator for analog integratingmultiple times a voltage waveform corresponding to the data obtained byadding up these plurality of step functions.
 2. A digital-to-analogconverter comprising: a plurality of data holding sections for holdingfor predetermined periods of time each of plural digital data to beinput at a predetermined interval; a plurality of step functiongenerators for generating a predetermined step function corresponding todigital data held in the plurality of data holding sections respectivelyin synchronization with each timing of inputting the plurality ofdigital data; an adding section for adding a value of the step functiongenerated by each of the step function generators; a step voltagewaveform generator for generating a stepwise analog voltagecorresponding to the digital data obtained by adding process performedby the adding section; and an integrator for analog integrating multipletimes an analog voltage generated by the step voltage waveformgenerators.
 3. The digital-to-analog converter according to claim 2,wherein said step function has values obtained by differentiating eachof piecewise polynomials multiple times, when a sampling function isconfigured by said piecewise polynomials.
 4. The digital-to-analogconverter according to claim 3, wherein said sampling function isdifferentiable only once over the whole region and has values of localsupport.
 5. The digital-to-analog converter according to claim 4,wherein said sampling function is a function of local support havingvalues other than zero in a range where the sample point t is from −2 to+2, and said sampling function is defined such that: (−t ²−4t−4)/4 for−2≦t<−3/2, (3t ²+8t+5)/4 for −3/2≦t<−1, (5t ²+12t+7)/4 for −1≦t<−1/2,(−7t ²+4)/4 for −1/2≦t<1/2, (5t ²−12t+7)/4 for 1/2≦t<1, (3t ²−8t+5)/4for 1≦t<3/2, and (−t ²+4t−4)/4 for 3/2≦t≦2.
 6. The digital-to-analogconverter according to claim 5, wherein two analog integral operationsare performed, and a continuous analog signal that connects smoothly thevoltages corresponding to the plural of digital data is generated. 7.The digital-to-analog converter according to claim 4, wherein two analogintegral operations are performed, and a continuous analog signal thatconnects smoothly the voltages corresponding to the plural of digitaldata is generated.
 8. The digital-to-analog converter according to claim2, wherein said step function comprises a positive region and a negativeregion set to have an equal area.
 9. The digital-to-analog converteraccording to claim 2, wherein said step function consists of eightpiecewise sections in equal width with a weight of −1, +3, +5, −7, −7,+5, +3, and −1 in a predetermined range corresponding to said fivedigital data arranged at an equal interval.
 10. The digital-to-analogconverter according to claim 2, wherein said step function implementsthe weighting by making the multiplication of −2, +2, +4, −8, −8, +4, +2and −2 by the bit shift and adding said digital data itself to a resultof multiplication.